DESCRIPTION
I Single 3.3V or 5V power supply
I Up to 3.2Gbps operation
I Low noise 50
CML data outputs; 60ps edge rates
I 1ps(p-p) max DJ, 1ps(rms) max RJ
I OC-TTL SD output with internal 5k
pull-up resistor
I TTL EN input
I Internal input 50
termination at inputs and outputs
I Programmable SD level set
I Available in a tiny 10-pin (3mm) MSOP and 16-pin
MLFTM (3mm x 3mm) packages
FEATURES
3.3V/5V 3.2Gbps CML LOW POWER
LIMITING POST AMPLIFIER w/TTL SD
SY88983V
FINAL
APPLICATIONS
I 1.25Gbps and 2.5Gbps Gigabit Ethernet
I 1062Mbps and 2Gbps Fibre Channel
I 155Mbps, 622Mbps and 2.5Gbps SONET/SDH
I Gigabit interface converter (GBIC)
I Small form factor transceivers
I Parallel 10G Ethernet
I High-gain line driver and line receiver
1
Rev.: A
Amendment: /0
Issue Date:
December 2002
MLFTM and
Micro LeadFrame are trademarks of Amkor Technology, Inc.
The SY88983V low-power limiting post amplifier is
designed for use in fiber optic receivers. The device connects
to typical transimpedance amplifiers (TIAs). The linear signal
output from TIAs can contain significant amounts of noise
and may vary in amplitude over time. The SY88983V
quantizes these signals and outputs typically 800mVp-p
voltage-limited waveforms.
The SY88983V operates from a single +3.3V or +5V
power supply, over temperatures ranging from 40
C to
+85
C. With its wide bandwidth and high gain, signals with
data rates up to 3.2Gbps and as small as 5mVp-p can be
amplified to drive devices with CML inputs or AC-coupled
PECL inputs.
The SY88983V generates a signal detect (SD) open-
collector TTL output with internal 5k
pull-up resistor. A
programmable signal detect level set pin (SD
LVL
) sets the
sensitivity of the input amplitude detection. SD asserts high
if the input amplitude rises above the threshold set by SD
LVL
and deasserts low otherwise. SD can be fed back to the
enable (EN) input to maintain output stability under a loss
of signal condition. EN deasserts the true output signal
without removing the input signal. Typically 4.6dB SD
hysteresis is provided to prevent chattering.
TYPICAL APPLICATIONS CIRCUIT
V
CC
EN
GND
To
CDR
SY88983V
200k
0.1
F
From
Transimpedance
Amp.
D
OUT
/D
OUT
V
REF
V
CC
SD
LVL
D
IN
/D
IN
0.1
F
0.1
F
0.1
F
0.1
F
SD
2
SY88983V
Micrel
PACKAGE/ORDERING INFORMATION
Ordering Information
Package
Operating
Package
Part Number
Type
Range
Marking
SY88983VKI
K10-1
Industrial
983V
SY88983VKITR*
K10-1
Industrial
983V
SY88983VMI
MLF-16
Industrial
983V
SY88983VMITR*
MLF-16
Industrial
983V
*Tape and Reel
1
EN
DIN
/DIN
VREF
SDLVL
10 VCC
DOUT
/DOUT
SD
GND
9
8
7
6
2
3
4
5
10-Pin MSOP (K10-1)
1
2
3
4
12
11
10
9
16 15 14 13
5
6
7
8
DIN
GND
GND
/DIN
DOUT
GND
GND
/DOUT
VCC
SDL
VL
EN
VCC
VCC
SD
VREF
VCC
16-Pin MLFTM (MLF-16)
PIN DESCRIPTION
Pin Number
Pin Number
(MSOP)
(MLFTM)
Pin Name
Type
Pin Function
1
15
EN
TTL Input:
Enable: Deasserts true data output when low.
Default is high.
2
1
DIN
Data Input
True data input w/50
termination to V
REF
.
3
4
/DIN
Data Input
Complementary data input w/50
termination to V
REF
.
4
6
VREF
Reference Voltage: Placing a capacitor from V
REF
to V
CC
helps stablize SD
LVL
.
5
14
SDLVL
Input:
Signal Detect Level Set: A resistor from this pin to V
CC
sets
Default is
the threshold for the data input amplitude at which the SD
maximum sensitivity.
output will be asserted.
6
2, 3, 10, 11, EP
GND
Ground
Device ground.
7
7
SD
Open Collector
Signal Detect: Asserts high when the data input amplitude
TTL Output with
rises above the threshold set by SD
LVL
.
internal 5k
pullup
resistor
8
9
/DOUT
CML Output
Complementary data output.
9
12
DOUT
CML Output
True data output.
10
5, 8, 13, 16
VCC
Power Supply
Positive power supply.
3
SY88983V
Micrel
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
) ....................................... 0V to +7.0V
Enable Voltage (EN) .............................................. 0 to V
CC
Signal Detect Level Set Voltage
(SD
LVL
) ............................................. (V
CC
1.3V) to V
CC
Data Input Continuous Current (D
IN
, /D
IN
) ................... 1mA
Data Output Current (D
OUT
, /D
OUT
) ........................... 13mA
Signal Detect Current (SD) .......................................... 5mA
V
REF
Current (V
REF
) .................................................... 1mA
Storage Temperature (T
S
) ....................... 55
C to +125C
Operating Ratings
(Note 2)
Supply Voltage (V
CC
) .............................. +3.0V to +3.6V or
............................................................ +4.5V to +5.5V
Ambient Temperature (T
A
) ......................... 40
C to +85C
Junction Temperature (T
J
) ....................... 40
C to +120C
Package Thermal Resistance
MLFTM
(
JA
) Still-Air .................................................... 59
C/W
(
JB
) Still-Air .................................................... 32
C/W
MSOP
(
JA
) Still-Air .................................................. 113
C/W
(
JB
) Still-Air .................................................... 74
C/W
V
CC
= 3.0V to 3.6V or 4.5V to 5.5V; R
LOAD
= 50
to V
CC
; T
A
= 40
C to +85C; typical values at V
CC
= 3.3V, T
A
= 25
C
Symbol
Parameter
Condition
Min
Typ
Max
Units
I
CC
Power Supply Current, Note 1
3.3V range
19
28
mA
5V range
21
31
mA
I
CC
Power Supply Current, Note 2
3.3V range
32
47
mA
5V range
38
48
mA
V
REF
V
REF
Voltage
V
CC
1.3
V
SD
LVL
SD
LVL
Level
V
CC
1.3
V
CC
V
V
OH
SD Output HIGH Level
Sourcing 100
A
2.4
V
CC
V
V
OL
SD Output LOW Level
Sinking 2mA
0.5
V
V
IH
EN Input HIGH Voltage
2.0
V
V
IL
EN Input LOW Voltage
0.8
V
I
IH
EN Input HIGH Current
V
IN
= 2.7V
20
A
V
IN
= V
CC
100
A
I
IL
EN Input LOW Current
V
IN
= 0.5V
0.3
mA
V
OH
Output HIGH Voltage
Note 3
V
CC
0.020 V
CC
0.005
V
CC
V
V
OL
Output LOW Voltage
Note 3
V
CC
0.400 V
CC
0.275
V
V
OFFSET
Differential Output Offset
80
mV
Z
O
Single-Ended Output Impedance
40
50
60
Note 1.
Excludes current of CML output stage. See "
Detailed Description."
Note 2.
Total device current with no output load.
Note 3.
Output levels are based on a 50
to V
CC
load impedance. If the load impedance is different, the output level will be changed.
DC ELECTRICAL CHARACTERISTICS
Note 1.
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. This is a stress rating only and functional operation is
not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to ABSOLUTE MAXIMUM RATlNG
conditions for extended periods may affect device reliability.
Note 2.
The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
4
SY88983V
Micrel
V
CC
= 3.0V to 3.6V or 4.5V to 5.5V; R
LOAD
= 50
to V
CC
; T
A
= 40
C to +85C; typical values at V
CC
= 3.3V, T
A
= 25
C.
Symbol
Parameter
Condition
Min
Typ
Max
Units
HYS
SD Hysteresis
Note 1
2
4.6
8
dB
t
OFF
SD Release Time
0.1
0.5
s
t
ON
SD Assert Time
0.2
0.5
s
t
r
,t
f
Differential Output Rise/Fall Time
60
120
ps
(20% to 80%)
Note 2
t
JITTER
Deterministic (p-p)
Note 3
1
ps
Random (rms)
1
ps
V
ID
Differential Input Voltage Swing
5
1800
mVp-p
V
IS
Single-Ended Input Voltage Swing
5
900
mVp-p
V
OD
Differential Output Voltage Swing
Note 4
550
800
mVp-p
V
SR
SD Sensitivity Range
10
50
mVp-p
A
V(Diff)
Differential Voltage Gain
38
dB
B
3dB
3dB Bandwidth
2.2
GHz
S
21
Single-Ended Small Signal-Gain
26
32
dB
Note 1.
Electrical signal.
Note 2.
With input signal V
ID
> 50mVp-p and 50
load.
Note 3.
Measured using K28.5 pattern at 2.488Gbps, V
ID
= 100mVp-p
Note 4.
Input is a 200MHz square wave, t
r
< 300ps, 50
load. V
ID
> 10mVp-p
AC ELECTRICAL CHARACTERISTICS
TYPICAL OPERATING CHARACTERISTICS
0
10
20
30
40
50
60
70
80
90
10
100
1000
10000 100000
V
ID
(mV
P-P
)
R
SDLVL
SD Assert/Deassert Level
vs. R
SDLVL
ASSERT
DEASSERT
5
SY88983V
Micrel
DETAILED DESCRIPTION
The SY88983V low power limiting post amplifier operates
from a single +3.3V or +5V power supply, over temperatures
from 40
C to +85C. Signals with data rates up to 3.2Gbps
and as small as 4mVp-p can be amplified. Figure 1 shows
the allowed input voltage swing. The SY88983V generates
an SD output, allowing feedback to EN for output stability.
SD
LVL
sets the sensitivity of the input amplitude detection.
Input Amplifier/Buffer
The SY88983V's inputs are internally terminated with 50
to V
CC
1.3V. Unless they are not affected by this internal
termination scheme, upstream devices need to be AC-
coupled to the SY88983V's inputs. Figure 2 shows a
simplified schematic of the input stage.
The high sensitivity of the input amplifier allows signals
as small as 5mVp-p to be detected and amplified. The input
amplifier allows input signals as large as 1800mVp-p. Input
signals are linearly amplified with a typically 38dB differential
voltage gain. Since it is a limiting amplifier, the SY88983V
outputs typically 800mVp-p voltage-limited waveforms for
input signals that are greater than 10mVp-p. Applications
requiring the SY88983V to operate with high-gain should
have the upstream TIA placed as close as possible to the
SY88983V's input pins to ensure the best performance of
the device.
Output Buffer
The SY88983V's CML output buffer is designed to drive
50
lines. The output buffer requires appropriate termination
for proper operation. An external 50
resistor to V
CC
or
equivalent for each output pin provides this. Figure 3 shows
a simplified schematic of the output stage and includes an
appropriate termination method. Of course, driving a
downstream device with a CML input that is internally
terminated with 50
to V
CC
eliminates the need for external
termination. As noted in the previous section, the amplifier
outputs typically 800mVp-p waveforms across 25
total
loads. The output buffer thus switches typically 16mA tail-
current. Figure 4 shows the power supply current
measurement which excludes the 16mA tail-current.
Signal Detect
The SY88983V generates a chatter-free signal detect
(SD) open-collector TTL output with internal 5k
pull-up
resistor as shown in Figure 5. SD is used to determine that
the input amplitude large enough to be considered a valid
input. SD asserts high if the input amplitude rises above the
threshold set by SD
LVL
and deasserts low otherwise. SD
can be fed back to the enable (EN) input to maintain output
stability under a loss of signal condition. EN deasserts low
the true output signal without removing the input signals.
Typically 4.6dB SD hysteresis is provided to prevent
chattering.
Signal Detect-Level Set
A programmable signal detect-level set pin (SD
LVL
) sets
the threshold of the input amplitude detection. Connecting
an external resistor between V
CC
and SD
LVL
sets the voltage
at SD
LVL
. This voltage ranges from V
CC
to
V
CC
1.3V. The external resistor creates a voltage divider
between V
CC
and V
CC
1.3V as shown in Figure 6. If desired,
an appropriate external voltage may be applied rather than
using a resistor. The smaller the external resistor, implying
a smaller voltage difference from SD
LVL
to V
CC
, lowers the
SD sensitivity. Hence, larger input amplitude is required to
assert SD.
Typical Operating Characteristics shows the
relationship between the input amplitude detection sensitivity
and the SD
LVL
setting resistor.
Hysteresis
The SY88983V provides typically 4.6dB SD electrical
hysteresis. By definition, a power ratio measured in dB is
10log(power ratio). Power is calculated as V
2
IN
/R for an
electrical signal. Hence the same ratio can be stated as
20log(voltage ratio). While in linear mode, the electrical
voltage input changes linearly with the optical power and
hence the ratios change linearly. Therefore, the optical
hysteresis in dB is half the electrical hysteresis in dB given
in the datasheet. The SY88983V provides typically 2.3dB
SD optical hysteresis. As the SY88983V is an electrical
device, this datasheet refers to hysteresis in electrical terms.
With 4.6dB SD hysteresis, a voltage factor of 1.7 is required
to assert or deassert SD.
PDF 
ZIP